The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2020
Filed:
Jun. 22, 2017
Applicant:
Svagos Technik, Inc., Santa Clara, CA (US);
Inventors:
Tirunelveli S. Ravi, Saratoga, CA (US);
Stephen Daniel Miller, San Jose, CA (US);
Assignee:
Svagos Technik, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/263 (2006.01); C30B 33/06 (2006.01); H01L 21/304 (2006.01); C30B 25/18 (2006.01); C30B 29/06 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7813 (2013.01); C30B 25/186 (2013.01); C30B 29/06 (2013.01); C30B 33/06 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/02381 (2013.01); H01L 21/02513 (2013.01); H01L 21/02532 (2013.01); H01L 21/263 (2013.01); H01L 21/2636 (2013.01); H01L 21/304 (2013.01);
Abstract
Methods and equipment for the removal of semiconductor wafers grown on the top surface of a single crystal silicon substrate covered by a porous silicon separation layer by using IR irradiation of the porous silicon separation layer to initiate release of the semiconductor wafer from the substrate, particularly at edges (and corners) of the top surface of the substrate.