The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Jun. 20, 2018
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Sonu Daryanani, Tempe, AZ (US);

Matthew G. Martin, Gilbert, AZ (US);

Gilles Festes, Fuveau, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/4074 (2006.01); G11C 11/56 (2006.01); H01L 27/11521 (2017.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0425 (2013.01); G11C 11/4074 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); H01L 27/11521 (2013.01); H01L 29/66825 (2013.01);
Abstract

Embodiments of the present disclosure provide systems and methods for improving the read window in a split-gate flash memory cell, e.g., by biasing the control gate terminal with a non-zero (positive or negative) voltage during cell read operations to improve or control the erased state read performance or the programmed state read performance of the cell. A method of operating a split-gate flash memory cell may include performing program operations, performing erase operations, and performing read operations in the cell, wherein each read operation includes applying a first non-zero voltage to the word line, applying a second non-zero voltage to the bit line, and applying a third non-zero voltage Vto the control gate.


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