Apparatus and method for handling address decoding in a system-on-chip

Abstract

An apparatus and method are provided for handling address decoding in a system-on-chip (SoC). The SoC has processing circuitry for performing data processing operations, a first plurality of devices, and an interconnect to couple the processing circuitry to the first plurality of devices. The first plurality of devices are a first level of devices within a hierarchical structure of devices forming a device network. Those devices communicate using a device communication protocol which also provides an enumeration mechanism to enable software executed on the processing circuitry to discover and configure the devices within the network. The system address space provides a pool of addresses that are reserved for allocation to the first plurality of devices. An address decoder of the SoC has a device address decoder to maintain, for each device in the first plurality of devices, an indication of which addresses within the pool are allocated to that device. Hence, when a request is issued by the processing circuitry identifying an address within the pool of addresses, the device address decoder can be used to determine the appropriate device within the first plurality of devices that the request is directed to. The device address decoder is exposed to the software as a device of the device network so as to enable the software executing on the processing circuitry to discover and configure the device address decoder using the enumeration mechanism. As a result, the allocation of the pool of addresses amongst the first plurality of devices can be dynamically reconfigured under software control.