Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator

Abstract

An integrated circuit for a coherent data processing system includes a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes request logic that communicates memory access requests and request responses with the accelerator unit via the second communication interface. A request response identifies a target of a corresponding memory access request utilizing a host tag specifying an entry associated with the target in the real address-based directory.