Error correction code decoders, semiconductor memory devices and memory systems

Abstract

An error correction code (ECC) decoder of a semiconductor memory device is provided. The ECC decoder includes an ECC checker, a syndrome generator, and an error detection/correction circuit. The ECC checker generates characteristic information representing first error information associated with message bits in an input codeword that is read from a target page in a memory cell array. The syndrome generator outputs a syndrome vector representing second error information associated with the input codeword by performing an operation on the message bits and parity bits in the input codeword based on a parity check matrix. The an error detection/correction circuit generates a transmission codeword by selectively correcting an error bit in the input codeword based on the characteristic information and the syndrome vector, generates a flag signal indicating whether the transmission codeword includes an error bit, and outputs a transmission message based on the transmission codeword.