The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

May. 15, 2018
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Sankaran M. Menon, Austin, TX (US);

Bradley H. Smith, Vancouver, WA (US);

Jinshi Huang, Fremont, CA (US);

Rolf H. Kuehnis, Portland, OR (US);

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G01R 31/3177 (2006.01); H04W 4/80 (2018.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/31703 (2013.01); G01R 31/31705 (2013.01); G01R 31/31722 (2013.01); H04W 4/80 (2018.02);
Abstract

Existing multi-wire debugging protocols, such as 4-wire JTAG, 2-wire cJTAG, or ARM SWD, are run through a serial wireless link by providing the debugger and the target device with hardware interfaces that include UARTs and conversion bridges. The debugger interface serializes outgoing control signals and de-serializes returning data. The target interface de-serializes incoming control signals and serializes outgoing data. The actions of the interfaces are transparent to the inner workings of the devices, allowing re-use of existing debugging software. Compression, signal combining, and other optional enhancements increase debugging speed and flexibility while wirelessly accessing target devices that may be too small, too difficult to reach, or too seal-dependent for a wired connection.


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