The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Oct. 30, 2019
Applicant:

Panasonic Intellectual Property Management Co., Ltd., Osaka, JP;

Inventors:

Takeyoshi Tokuhara, Osaka, JP;

Sanshiro Shishido, Osaka, JP;

Masaaki Yanagida, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 5/378 (2011.01); H01L 27/146 (2006.01); H04N 5/355 (2011.01); H01L 27/30 (2006.01); H01L 51/00 (2006.01);
U.S. Cl.
CPC ...
H04N 5/378 (2013.01); H01L 27/146 (2013.01); H01L 27/14612 (2013.01); H01L 27/14665 (2013.01); H01L 27/14667 (2013.01); H01L 27/307 (2013.01); H04N 5/35563 (2013.01); H01L 51/0046 (2013.01); H01L 51/0061 (2013.01); H01L 51/0068 (2013.01); H01L 51/0071 (2013.01); H01L 51/0072 (2013.01); H01L 51/0073 (2013.01); H01L 51/0078 (2013.01);
Abstract

An imaging device including a first imaging cell having a first photoelectric converter including a first electrode, a second electrode, and a first photoelectric conversion layer between the first electrode and the second electrode, and a first reset transistor one of a source and a drain of which is coupled to the first electrode; and a second imaging cell having a second photoelectric converter including a third electrode, a fourth electrode, and a second photoelectric conversion layer between the third electrode and the fourth electrode, and a second reset transistor one of a source and a drain of which is coupled to the third electrode. The imaging device further including a first voltage supply circuitry to supply a first voltage to the first reset transistor; and a second voltage supply circuitry to supply a second voltage different from the first voltage to the second reset transistor.


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