The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Sep. 29, 2016
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Ashoke Ravi, Hillsboro, OR (US);

Rotem Banin, Even Yehuda, IL;

Ofir Degani, Haifa, IL;

David Ben-Haim, Shoham, IL;

Yigal Kalmanovich, Haifa, IL;

Assignee:

INTEL IP CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/08 (2006.01); H03L 7/099 (2006.01); H03L 7/093 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0995 (2013.01); H03L 7/093 (2013.01); H04L 7/0331 (2013.01); H04L 7/08 (2013.01); H03L 2207/50 (2013.01);
Abstract

For example, a digital PLL may include a digitally controlled Ring Oscillator (DCRO) configured to generate a frequency output based on a control signal, the DCRO comprising a plurality of stages in a cyclic order, a first stage of the plurality of stages comprising a plurality of inverter modules controlled by the control signal and comprising a plurality of outputs that drive inputs of a plurality of second stages in the plurality of stages; a decoder to decode a phase of the DCRO based on a plurality of sampled phases of the plurality of stages of the DCRO; and a phase error estimator to estimate a phase error based on the phase of the DCRO and a frequency control word, the control signal is based on the phase error.


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