The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Dec. 09, 2019
Applicant:

Bae Systems Information and Electronic Systems Integration Inc., Nashua, NH (US);

Inventors:

Joseph D. Cali, Nashua, NH (US);

Curtis M. Grens, Manchester, NH (US);

Richard L. Harwood, Westford, MA (US);

Gary M. Madison, Waltham, MA (US);

James M. Meredith, Westford, MA (US);

Zachary D. Schottmiller, Nashua, NH (US);

Randall M. White, Merrimack, NH (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/135 (2006.01); H03K 5/133 (2014.01); H03L 7/081 (2006.01); H03L 7/07 (2006.01); H03L 7/08 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0814 (2013.01); G06F 1/10 (2013.01); H03K 5/133 (2013.01); H03K 5/135 (2013.01); H03L 7/07 (2013.01); H03L 7/0805 (2013.01);
Abstract

A clock alignment system includes a first clock generator generating a first clock signal in a first clock domain and a second clock generator generating a second clock signal in a second clock domain slower than the first clock domain. A coarse delay-locked loop (DLL) generates third clock signals having corresponding phase offsets from the first clock signal, and a fine DLL generates a fourth clock signal by adjusting the phase of a selected one of the third clock signals. The second clock generator generates the second clock signal from the fourth clock signal. A phase detector compares phases of the first and second clock signals. A control circuit aligns the first and second clock signals by using the compared phases to select the third clock signal output by the coarse DLL, and control the phase adjustment by the fine DLL of this third clock signal.


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