The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Mar. 11, 2019
Applicant:

Inphi Corporation, Santa Clara, CA (US);

Inventors:

Rahul Shringarpure, Santa Clara, CA (US);

Tom Peter Edward Broekaert, Santa Clara, CA (US);

Gaurav Mahajan, Santa Clara, CA (US);

Assignee:

INPHI CORPORATION, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/08 (2006.01); H03F 3/45 (2006.01); H04B 10/61 (2013.01); H04B 10/69 (2013.01); H03F 1/02 (2006.01);
U.S. Cl.
CPC ...
H03F 3/082 (2013.01); H03F 1/0205 (2013.01); H03F 3/087 (2013.01); H03F 3/45179 (2013.01); H03F 3/45475 (2013.01); H04B 10/616 (2013.01); H04B 10/693 (2013.01); H03F 2200/555 (2013.01);
Abstract

A transimpedance amplifier (TIA) device. The device includes a photodiode coupled to a differential TIA with a first and second TIA, which is followed by a Level Shifting/Differential Amplifier (LS/DA). The photodiode is coupled between a first and a second input terminal of the first and second TIAs, respectively. The LS/DA can be coupled to a first and second output terminal of the first and second TIAs, respectively. The TIA device includes a semiconductor substrate comprising a plurality of CMOS cells, which can be configured using 28 nm process technology to the first and second TIAs. Each of the CMOS cells can include a deep n-type well region. The second TIA can be configured using a plurality CMOS cells such that the second input terminal is operable at any positive voltage level with respect to an applied voltage to a deep n-well for each of the plurality of second CMOS cells.


Find Patent Forward Citations

Loading…