The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2020
Filed:
Feb. 09, 2017
B. G. Negev Technologies and Applications Ltd., AT Ben-gurion University, Beer Sheva, IL;
Abstract
A plug-and-play Transient Suppression Unit (TSU) for Voltage Regulator Modules (VRMs), which comprises a bi-directional current source connected via a high voltage port and a low voltage port of the TSU in parallel to a voltage output of the VRM, adapted to immediately sink or source current supplied to a load; a detection circuit for detecting mismatches between the voltage output of the VRM to a reference steady-state voltage, which comprises a first comparator for detecting a match between the voltage output of the VRM to the reference steady-state voltage; a second comparator for detecting a mismatch between the voltage output of the VRM to a predefined threshold higher than the reference steady-state voltage; a third comparator for detecting a mismatch between the voltage output of the VRM to a predefined threshold lower than the reference steady-state voltage value; a transient response accelerator, connected via a third port of the TSU to the output compensation port of the VRM error amplifier, and adapted to control duty-ratio saturation of the VRM. A loading transient is detected by the third comparator, upon which the VRM's duty ratio is saturated to a maximal value by the transient response accelerator and current is sourced from the current source to the output, until the first comparator detects that the voltage output of the VRM matches the expected steady-state voltage. An unloading transient is detected by the second comparator, upon which the VRM's duty ratio is saturated to a minimal value by the transient response accelerator and current is sunk from the output into the current source, until the first comparator detects that the voltage output of the VRM matches the expected steady-state voltage.