The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Feb. 27, 2019
Applicant:

Socionext Inc., Kanagawa, JP;

Inventors:

Toshio Hino, Yokohama, JP;

Junji Iwahori, Yokohama, JP;

Assignee:

SOCIONEXT INC., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/118 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 27/06 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 27/0207 (2013.01); H01L 27/0629 (2013.01); H01L 29/78 (2013.01); H01L 2027/11812 (2013.01); H01L 2027/11862 (2013.01); H01L 2027/11866 (2013.01); H01L 2027/11881 (2013.01); H01L 2027/11892 (2013.01);
Abstract

The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.


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