The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

May. 24, 2017
Applicant:

Denso Corporation, Kariya, JP;

Inventors:

Takafumi Arakawa, Kariya, JP;

Shigeki Takahashi, Kariya, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 27/07 (2006.01); H01L 29/06 (2006.01); H01L 29/861 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/32 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0664 (2013.01); H01L 27/0727 (2013.01); H01L 29/0619 (2013.01); H01L 29/0623 (2013.01); H01L 29/0692 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/32 (2013.01); H01L 29/7397 (2013.01); H01L 29/78 (2013.01); H01L 29/8611 (2013.01);
Abstract

A semiconductor device has a semiconductor substrate including an IGBT region operating as an IGBT provided by an emitter layer, a base layer, a drift layer and a collector layer, and a diode region operating as a diode and provided by an anode layer, the drift layer and a cathode layer. The semiconductor substrate further includes a guard ring of a second conduction type, provided in a surface layer of the drift layer in a peripheral region surrounding a device region where the IGBT region and the diode region are adjacent to each other. The cathode layer and the guard ring are positioned such as to satisfy L/d≥1.5, where L is a minimum value of a distance between the cathode layer and the guard ring as projected to a plane parallel to a surface of the semiconductor substrate, and d is a thickness of the semiconductor substrate.


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