The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2020
Filed:
Jun. 19, 2019
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Moon Ki Jung, Seoul, KR;
Boh Chang Kim, Suwon-si, KR;
Assignee:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 17/16 (2006.01); H01L 23/525 (2006.01); G11C 17/18 (2006.01); G11C 29/50 (2006.01); H01L 27/112 (2006.01); G11C 29/24 (2006.01); H01F 10/32 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 43/02 (2006.01);
U.S. Cl.
CPC ...
G11C 17/16 (2013.01); G11C 17/18 (2013.01); G11C 29/24 (2013.01); G11C 29/50 (2013.01); H01L 23/5252 (2013.01); H01L 27/11206 (2013.01); G11C 11/161 (2013.01); G11C 11/1675 (2013.01); G11C 13/0004 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); G11C 2013/0078 (2013.01); H01F 10/329 (2013.01); H01L 27/2427 (2013.01); H01L 43/02 (2013.01); H01L 45/06 (2013.01); H01L 45/126 (2013.01); H01L 45/1233 (2013.01); H01L 45/144 (2013.01);
Abstract
A memory device includes a memory cell array including a plurality of memory cells and a memory controller to control the plurality of memory cells. The memory cell array has a first fuse region including a plurality of first fuse cells having a same structure as the plurality of memory cells and a second fuse region including a plurality of second fuse cells having a structure different from a structure of the plurality of memory cells. The memory controller has a fuse selection circuit selecting one of the first fuse region and the second fuse region.