The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2020
Filed:
Sep. 11, 2019
Applicant:
Toshiba Memory Corporation, Minato-ku, JP;
Inventors:
Hiroshi Maejima, Tokyo, JP;
Katsuaki Isobe, Yokohama, JP;
Naohito Morozumi, Kawasaki, JP;
Go Shikata, Moriya, JP;
Susumu Fujimura, Yokohama, JP;
Assignee:
Toshiba Memory Corporation, Minato-ku, JP;
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); H01L 27/11565 (2017.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 27/11519 (2017.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); H01L 27/11519 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract
According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.