The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Apr. 30, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Abhishek Joshi, San Jose, CA (US);

Grigor S. Gasparyan, San Jose, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/327 (2020.01); G06F 30/3323 (2020.01); G06F 111/04 (2020.01); G06F 111/20 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/3323 (2020.01); G06F 2111/04 (2020.01); G06F 2111/20 (2020.01);
Abstract

An example method for compiling by a processor-based system includes obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; generating a global mapping of the program nodes based on a representation of the array of data processing engines; generating a detailed mapping of the program nodes based on the global mapping, the detailed mapping assigning input/outputs of programmable logic (PLIOs) of the device to channels in an interface of the array of data processing engines, the detailed mapping further assigning buffers of the application to individual memory banks in the array of data processing engines; and translating the detailed mapping to a file.


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