The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Apr. 11, 2018
Applicant:

Wiwynn Corporation, New Taipei, TW;

Inventors:

Pei-Ling Yu, New Taipei, TW;

Chia-Liang Hsu, New Taipei, TW;

Bing-Kun Syu, New Taipei, TW;

Assignee:

Wiwynn Corporation, New Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 3/06 (2006.01); G06F 13/42 (2006.01); G06F 9/00 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 3/061 (2013.01); G06F 3/067 (2013.01); G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0664 (2013.01); G06F 9/00 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A processing method of data redundancy is utilized for a Non-Volatile Memory express (NVMe) to transfer data via a fabric channel from a host terminal to a Remote-direct-memory-access-enable Network Interface Controller (RNIC) and a Just a Bunch of Flash (JBOF). The processing method comprises virtualizing a Field Programmable Gate Array (FPGA) of the RNIC into a Dynamic Random Access Memory (DRAM) and storing the data to the DRAM; replicating or splitting the data into a plurality of data packets and reporting a plurality of virtual memory addresses corresponding to the plurality of data packets to the RNIC by the FPGA; and reading and transmitting the plurality of data packets to a plurality of corresponding NVMe controllers according to the plurality of virtual memory addresses; wherein the FPGA reports to the RNIC that a memory size of the FPGA is larger than that of the DRAM.


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