The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

May. 30, 2018
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Michael W. Boyer, Bellevue, WA (US);

Onur Kayiran, Santa Clara, CA (US);

Yasuko Eckert, Bellevue, WA (US);

Steven Raasch, Boxborough, MA (US);

Muhammad Shoaib Bin Altaf, Austin, TX (US);

Assignee:

ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0815 (2016.01); G06F 12/1045 (2016.01); G06F 12/0888 (2016.01); G06F 12/126 (2016.01); G06F 3/12 (2006.01); G06F 9/50 (2006.01); G06F 13/18 (2006.01); G06F 13/30 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 12/0888 (2013.01); G06F 12/1045 (2013.01); G06F 3/1263 (2013.01); G06F 9/5038 (2013.01); G06F 12/126 (2013.01); G06F 13/18 (2013.01); G06F 13/30 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/657 (2013.01); G06F 2212/684 (2013.01);
Abstract

A miss in a cache by a thread in a wavefront is detected. The wavefront includes a plurality of threads that are executing a memory access request concurrently on a corresponding plurality of processor cores. A priority is assigned to the thread based on whether the memory access request is addressed to a local memory or a remote memory. The memory access request for the thread is performed based on the priority. In some cases, the cache is selectively bypassed depending on whether the memory access request is addressed to the local or remote memory. A cache block is requested in response to the miss. The cache block is biased towards a least recently used position in response to requesting the cache block from the local memory and towards a most recently used position in response to requesting the cache block from the remote memory.


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