Hierarchical clock scaling in a data storage controller

Abstract

The present disclosure describes technologies and techniques for use by a data storage controller—such as a non-volatile memory (NVM) controller—to adaptively and hierarchically scale clock signals distributed to its internal components. In various examples described herein, the data storage controller is configured to downscale the internal clocks of the controller for all processing sub-blocks that are in an Active Idle state (or in similar idle states where a component is active but has no tasks to perform). When an entire hierarchy of components is idle, the clock signal applied to the entire hierarchy is downscaled. By downscaling the clock for an entire hierarchy of components, power consumed by the corresponding clock tree is also reduced. In specific examples, clock signals are downscaled by a factor of thirty-two to reduce power consumption. NVMe examples are provided herein.