The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Sep. 25, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

David M. Mahoney, Gilroy, CA (US);

Joseph M. Juane, San Jose, CA (US);

Owais E. Malik, San Jose, CA (US);

Mohsen H. Mardi, Saratoga, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/69 (2020.01); G01R 1/04 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/69 (2020.01); G01R 1/0466 (2013.01); G01R 1/0483 (2013.01); G01R 31/28 (2013.01);
Abstract

Examples described herein provide for testing of a test socket using multiple insertions to a contact resistance (CRES) test system. In an example, the test socket is placed in a first orientation on an interface board electrically connected to a test system. Using the test system and through the interface board, a first subset of probes of the test socket is tested while the test socket is in the first orientation on the interface board. The test socket is placed in a second orientation different from the first orientation on the interface board. Using the test system and through the interface board, a second subset of probes of the test socket is tested while the test socket is in the second orientation on the interface board. At least some probes of the second subset of probes are different from the first subset of probes.


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