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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10834828 B1

PDFFull Text
Date of Patent:
Nov. 10, 2020

Filed:

Jan. 26, 2018

Creating inductors, resistors, capacitors and other structures in printed circuit board vias with light pipe technology

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Gerald Bartley, Rochester, MN (US);

Darryl Becker, Rochester, MN (US);

Matthew Doyle, Chatfield, MN (US);

Mark Jeanson, Rochester, MN (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Tutunjian & Bitetto, P.C.

Nathan Rau

Primary Examiner:

Daborah Chacko-Davis

Int. Cl.
CPC ...
G03F 1/20 (2012.01); G03F 7/20 (2006.01); H05K 3/30 (2006.01); H01F 41/04 (2006.01); H01F 17/00 (2006.01); H01F 27/28 (2006.01); G02B 6/46 (2006.01); H01B 1/02 (2006.01); H01F 27/06 (2006.01); H01G 2/06 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/40 (2006.01); G03F 1/00 (2012.01);
U.S. Cl.
CPC ...
H05K 3/301 (2013.01); G02B 6/46 (2013.01); G03F 7/70733 (2013.01); H01B 1/02 (2013.01); H01F 17/0013 (2013.01); H01F 17/0033 (2013.01); H01F 27/06 (2013.01); H01F 27/2804 (2013.01); H01F 41/042 (2013.01); H01F 41/046 (2013.01); H01G 2/06 (2013.01); H05K 1/115 (2013.01); H05K 1/184 (2013.01); H05K 3/4038 (2013.01); G03F 1/14 (2013.01); H01F 2017/002 (2013.01); H01F 2017/004 (2013.01); H01F 2027/065 (2013.01);
Abstract

A method for forming passive electrical devices that includes depositing a photo reactive layer over a sidewall of a via that extends through a printed circuit board; inserting a light pipe having a mask configured to provide a passive electronic device geometry within the via to an entire depth of the via; and exposing the photo reactive layer to radiation provided by the light pipe to provide a pattern having the passive electronic device geometry on the sidewall of the via.

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