The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Feb. 12, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Glenn Gilda, Binghamton, NY (US);

Arthur O'Neill, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/52 (2006.01); H03M 13/17 (2006.01); G06F 11/10 (2006.01); H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
H03M 13/175 (2013.01); G06F 11/1004 (2013.01); H03M 13/1575 (2013.01);
Abstract

Embodiments include methods, systems and circuits for operating an error trapping logic circuit in a memory device. Aspects include receiving, during a first clock cycle, data and check bits for the data from a memory location and determining, during the first clock cycle, whether the data includes any error by calculating an error syndrome from the data and the check bits. Aspects also include determining, during a second clock cycle, a type of the error based on a full decoding of the error syndrome. Aspects further include determining whether to store the data, the check bits and the error syndrome in trap registers of the error trapping logic circuit based on an operating mode of the error trapping logic circuit and the type of the error.


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