The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Dec. 12, 2018
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Richard L. Walke, Edinburgh, GB;

Andrew Dow, Edinburgh, GB;

Zahid Khan, Loanhead, GB;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/11 (2006.01); H03M 13/00 (2006.01); H03M 13/37 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
H03M 13/1105 (2013.01); G06F 11/1076 (2013.01); H03M 13/616 (2013.01);
Abstract

Low-density parity check (LDPC) decoder circuitry is configured to decode an input codeword using a plurality of circulant matrices of a parity check matrix for an LDPC code. Multiple memory banks are configured to store elements of the input codeword. A memory circuit is configured for storage of an instruction sequence. Each instruction describes for one of the circulant matrices, a corresponding layer and column of the parity check matrix and a rotation. Each instruction includes packing factor bits having a value indicative of a number of instructions of the instruction sequence to be assembled in a bundle of instructions. A bundler circuit is configured to assemble the number of instructions from the memory circuit in a bundle. The bundler circuit specifies one or more no-operation codes (NOPs) in the bundle in response to the value of the packing factor bits and provides the bundle to the decoder circuitry.


Find Patent Forward Citations

Loading…