The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2020
Filed:
Feb. 07, 2018
Mitsubishi Heavy Industries, Ltd., Tokyo, JP;
Japan Aerospace Exploration Agency, Tokyo, JP;
Daisuke Matsuura, Tokyo, JP;
Takanori Narita, Tokyo, JP;
Masahiro Kato, Tokyo, JP;
Daisuke Kobayashi, Kanagawa, JP;
Kazuyuki Hirose, Kanagawa, JP;
Osamu Kawasaki, Ibaraki, JP;
Yuya Kakehashi, Kanagawa, JP;
Taichi Ito, Kanagawa, JP;
MITSUBISHI HEAVY INDUSTRIES, LTD., Tokyo, JP;
JAPAN AEROSPACE EXPLORATION AGENCY, Tokyo, JP;
Abstract
An operation adjustment method of an SOI device comprises steps of: (a) obtaining a drain current-substrate bias voltage characteristic of an NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of a PMOS transistor as a voltage obtained by subtracting a built-in potential of a pn junction from the lowest substrate bias voltage; and (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit. Reduction in the power consumption and maintenance of the radiation tolerance are both achieved for the SOI device.