The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Mar. 18, 2019
Applicant:

Mitsubishi Electric Research Laboratories, Inc., Cambridge, MA (US);

Inventors:

Koon Hoo Teo, Lexington, MA (US);

Pin-Chun Shen, Cambridge, MA (US);

Chungwei Lin, Arlington, MA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); G11C 14/00 (2006.01); G06F 12/02 (2006.01); H01L 27/11597 (2017.01); H01L 27/11502 (2017.01); H01L 27/11585 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11597 (2013.01); G06F 12/0238 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 11/2297 (2013.01); G11C 14/009 (2013.01); G11C 14/0045 (2013.01); H01L 27/11502 (2013.01); H01L 27/11585 (2013.01);
Abstract

Devices and methods of a transistor device that include a flexible memory cell. The flexible memory cell having a gate stack with sidewalls provided over a substrate. The gate stack including a metal gate layer provided over the substrate. A buffer layer provided over the metal gate layer. A ferroelectric layer provided over the buffer layer. A dielectric layer provided over the ferroelectric layer. Further, a two-dimensional (2D) material layer provided over a portion of a top surface of the dielectric layer. Source and drain regions provided on separate portions of the top surface of the dielectric layer so as to create a cavity that the 2D material layer are located.


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