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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10833096 B1

PDFFull Text
Date of Patent:
Nov. 10, 2020

Filed:

Aug. 31, 2018

Semiconductor device

Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Ryo Tanaka, Yokkaichi, JP;

Hiroyuki Yamasaki, Nagoya, JP;

Hideaki Harakawa, Yokkaichi, JP;

Assignee:

Toshiba Memory Corporation, Minato-ku, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Mounir S Amer

Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/04 (2006.01); H01L 27/11565 (2017.01); H01L 29/16 (2006.01); H01L 27/1157 (2017.01); H01L 21/265 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 29/04 (2013.01); H01L 29/0649 (2013.01); H01L 29/1037 (2013.01); H01L 29/16 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/02636 (2013.01); H01L 21/26513 (2013.01); H01L 21/31116 (2013.01);
Abstract

According to one embodiment, a semiconductor device includes: a first pillar penetrating a first stack and including a first insulator, a first portion of a first semiconductor provided on an upper and an outer side surface of the first insulator, a second insulator provided on an outer side surface of the first portion, and a second portion being provided above the first stack, being coupled to an upper surface of the first portion, and including a lower surface greater than the upper surface of the first portion; an oxide film provided on a side surface of the second portion; and a second pillar penetrating a second stack and including a second semiconductor electrically coupled to the first semiconductor, and a third insulator on an outer side surface of the second semiconductor.

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