The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Dec. 21, 2016
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Huilong Zhu, Poughkeepsie, NY (US);

Yanbo Zhang, Beijing, CN;

Huicai Zhong, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/033 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 21/027 (2006.01); H01L 29/10 (2006.01); H01L 29/36 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0924 (2013.01); H01L 21/0338 (2013.01); H01L 21/28 (2013.01); H01L 21/31053 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 27/0207 (2013.01); H01L 29/0847 (2013.01); H01L 29/4232 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7848 (2013.01); H01L 29/7855 (2013.01); H01L 21/0273 (2013.01); H01L 27/0928 (2013.01); H01L 29/1083 (2013.01); H01L 29/36 (2013.01); H01L 29/66537 (2013.01);
Abstract

A semiconductor arrangement includes: a substrate; fins formed on the substrate and extending in a first direction; gate stacks formed on the substrate and each extending in a second direction crossing the first direction to intersect at least one of the fins, and dummy gates composed of a dielectric and extending in the second direction; spacers formed on sidewalls of the gate stacks and the dummy gates; and dielectric disposed between first and second ones of the gate stacks in the second direction to electrically isolate the first and second gate stacks. The dielectric is disposed in a space surrounded by respective spacers of the first and second gate stacks which extend integrally. At least a portion of an interval between the first and second gate stacks in the second direction is less than a line interval achievable by lithography in a process of manufacturing the semiconductor arrangement.


Find Patent Forward Citations

Loading…