The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Apr. 05, 2018
Applicant:

Synaptics Incorporated, San Jose, CA (US);

Inventor:

Dan Shen, Irvine, CA (US);

Assignee:

SYNAPTICS CORPORATION, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01); H01L 21/8238 (2006.01); H03F 3/217 (2006.01); H03F 3/185 (2006.01); H02M 3/155 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0921 (2013.01); H01L 21/823892 (2013.01); H01L 29/0619 (2013.01); H01L 29/1083 (2013.01); H02M 3/155 (2013.01); H03F 3/185 (2013.01); H03F 3/2173 (2013.01); H03F 2200/03 (2013.01);
Abstract

Systems and methods according to one or more embodiments are provided for improved reliability and efficiency of high side power stage output drivers used in switching amplifiers. In one example, a system includes a power device structure comprising an nwell structure formed within a semiconductor p substrate and a pwell structure formed within the nwell structure. The system further includes one or more NMOS electronic power devices formed on the pwell structure and a pwell guardring formed on the pwell structure configured to surround the one or more NMOS electronic power devices. The system further includes an nwell guardring formed on the nwell structure configured to surround the pwell structure and a p+ guardring formed on the nwell structure configured to surround the nwell guardring.


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