The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Mar. 29, 2016
Applicant:

Murata Manufacturing Co., Ltd., Nagaokakyo, JP;

Inventors:

Jahangir Afsharian, Markham, CA;

Bing Gong, Markham, CA;

Hussain S. Athab, Markham, CA;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01F 27/34 (2006.01); H01F 27/28 (2006.01); H01F 27/40 (2006.01); H01F 27/29 (2006.01); H02M 3/335 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 7/20 (2006.01); H02M 1/00 (2006.01); H01F 27/06 (2006.01);
U.S. Cl.
CPC ...
H01F 27/346 (2013.01); H01F 27/2804 (2013.01); H01F 27/29 (2013.01); H01F 27/40 (2013.01); H02M 3/33592 (2013.01); H05K 1/111 (2013.01); H05K 1/181 (2013.01); H05K 7/209 (2013.01); H01F 2027/065 (2013.01); H01F 2027/2819 (2013.01); H02M 3/335 (2013.01); H02M 2001/0058 (2013.01); H05K 2201/1003 (2013.01); Y02B 70/1433 (2013.01); Y02B 70/1491 (2013.01);
Abstract

A transformer assembly includes a transformer with primary windings located on multiple layers and with secondary windings interleaved with the multiple layers and includes a substrate connected to the transformer and with a first transistor with first, second, and third terminals, in which the first terminal is connected to the secondary windings, the second terminal is connected to an output terminal of the transformer assembly, and the third terminal is a control terminal; first conductive layers; second conductive layers interleaved with the first conductive layers; a first via that is solid filled and that connects the first conductive layers and the first terminal; and a second via that is solid filled and that connects the second conductive layers and the second terminal.


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