The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Sep. 30, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Gregory J. Fredeman, Wappingers Falls, NY (US);

Thomas E. Miller, Poughkeepsie, NY (US);

Dinesh Kannambadi, Wappingers Falls, NY (US);

Phil Paone, Rochester, MN (US);

Donald W. Plass, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G11C 11/4074 (2006.01); G11C 8/18 (2006.01); G11C 11/408 (2006.01); G11C 11/4076 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4074 (2013.01); G11C 5/145 (2013.01); G11C 5/147 (2013.01); G11C 8/18 (2013.01); G11C 11/4076 (2013.01); G11C 11/4085 (2013.01);
Abstract

Techniques for negative voltage generation for a computer memory are described herein. An aspect includes enabling a first negative word line voltage (VWL) clock generator. Another aspect includes providing, by the first VWL clock generator, based on a clock signal, a first pump clock signal to a first VWL pump, and a second pump clock signal to a second VWL pump. Another aspect includes generating a VWL based on the first VWL pump and the second VWL pump, wherein the VWL is provided to a word line driver of a computer memory module. Another aspect includes comparing the VWL to a VWL reference voltage. Another aspect includes, based on the VWL being below the VWL reference voltage, disabling the first VWL clock generator, wherein the first VWL pump and the second VWL pump are disabled based on disabling the first VWL clock generator.


Find Patent Forward Citations

Loading…