The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Nov. 13, 2018
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Jakob Raymond Jones, San Jose, CA (US);

Prasanna Padmanabhan, Fremont, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/34 (2020.01); H01L 27/115 (2017.01); G06F 15/80 (2006.01); H01L 27/02 (2006.01); H03K 19/17728 (2020.01); H01L 27/118 (2006.01); G06F 30/39 (2020.01); H01L 23/528 (2006.01); H01L 23/50 (2006.01); H01L 27/11 (2006.01); G06F 30/00 (2020.01); G06F 115/08 (2020.01);
U.S. Cl.
CPC ...
G06F 30/34 (2020.01); G06F 15/8015 (2013.01); G06F 30/39 (2020.01); H01L 27/0207 (2013.01); H01L 27/115 (2013.01); H01L 27/11807 (2013.01); H03K 19/17728 (2013.01); G06F 30/00 (2020.01); G06F 2115/08 (2020.01); H01L 23/50 (2013.01); H01L 23/528 (2013.01); H01L 27/1104 (2013.01); H01L 27/118 (2013.01);
Abstract

Systems and methods for reconfiguration of a hardened intellectual property (IP) block in an integrated circuit (IC) device are provided. Reconfiguration of the hardened IP block in the IC device may transition between functions supported by the hardened IP block. A transition may occur as a pre-configured profile is selected to reconfigure the hardened IP block. Further, configuration data associated with each of the pre-configured profiles of the hardened IP block may be generated and storage space to store the configuration data may be created. Additionally, reconfiguration control logic to read and implement the configuration data in hard IP design primitives may also be generated.


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