The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Sep. 27, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Ofer Geva, Ramat Hasaron, IL;

Shiran Raz, Ganey Tikva, IL;

Yaniv Maroz, Kiryat Uno, IL;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/398 (2020.01); G06F 30/30 (2020.01); G06F 30/33 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/30 (2020.01); G06F 30/33 (2020.01); G06F 30/398 (2020.01); G06F 2119/12 (2020.01);
Abstract

Generating a design of an integrated circuit by analyzing a physical design of an integrated circuit by determining, for a pin of a circuit of the integrated circuit, that a candidate timing constraint for signal arrival time at the pin is later than a current timing constraint for signal arrival time at the pin, determining that a slack value associated with the current timing constraint has a greater negative value than a predefined negative slack threshold value, determining that the current timing constraint is within a user-defined range of signal arrival time values associated with the pin, determining that the candidate timing constraint is earlier than a latest-allowable signal arrival time at the pin, setting the current timing constraint equal to the candidate timing constraint, and generating a revised physical design of the integrated circuit that incorporates the current timing constraint.


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