The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Aug. 14, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Jose Neves, Poughkeepsie, NY (US);

Adam Matheny, Hyde Park, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/394 (2020.01); G06F 119/06 (2020.01); G06F 30/3312 (2020.01); G06F 30/398 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/00 (2020.01); G06F 30/394 (2020.01); G06F 30/3312 (2020.01); G06F 30/398 (2020.01); G06F 2119/06 (2020.01); G06F 2119/12 (2020.01);
Abstract

Techniques for parallel power down processing of an integrated circuit (IC) design are described herein. An aspect includes receiving IC design information comprising a plurality of IC elements. Another aspect includes identifying a plurality of timing endpoints in the IC design information. Another aspect includes determining a plurality of nets, each net comprising a respective subset of the plurality of IC elements, based on the identified plurality of timing endpoints. Another aspect includes performing power down processing of net drivers in the plurality of nets, wherein the power down processing of at least a subset of the plurality of nets is performed in parallel.


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