The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10831889 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 10, 2020

Filed:

Aug. 13, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

William E. Hall, Clinton, CT (US);

Guerney D. H. Hunt, Yorktown Heights, NY (US);

Ronald N. Kalla, Round Rock, TX (US);

Jentje Leenstra, Bondorf, DE;

Paul Mackerras, Weston, AU;

William J. Starke, Round Rock, TX (US);

Jeffrey A. Stuecheli, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 21/55 (2013.01); G06F 9/455 (2018.01); G06F 21/53 (2013.01); G06F 12/14 (2006.01); G06F 13/40 (2006.01); G06F 13/364 (2006.01); G06F 21/78 (2013.01); G06F 21/62 (2013.01);
U.S. Cl.
CPC ...
G06F 21/556 (2013.01); G06F 9/45558 (2013.01); G06F 12/1441 (2013.01); G06F 13/364 (2013.01); G06F 13/404 (2013.01); G06F 21/53 (2013.01); G06F 21/78 (2013.01); G06F 21/6281 (2013.01); G06F 2009/45587 (2013.01); G06F 2212/1052 (2013.01); G06F 2221/034 (2013.01);
Abstract

A system, a method, and a computer program product for secure memory implementation for secure execution of virtual machines are provided. Data is processed in a first mode and a second mode, and commands are sent to a chip interconnect bus using real addresses, wherein the chip interconnect bus transports a number of bits for the real addresses. A memory controller is operatively coupled to a memory component. A secure memory range is specified by using range registers. If the real address is detected to be in the secure memory range to match a memory component address, a real address bit is set. If the real address is in the memory address hole, a security access violation is detected. If the real address is not in the secure address range and the real address bit is set, the security access violation is detected.


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Hall, William. (2020). Secure memory implementation for secure execution of virtual machines (U.S. Patent No. 10831889). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10831889

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