The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Jun. 28, 2018
Applicant:

Emc Ip Holding Company Llc, Hopkinton, MA (US);

Inventors:

Liam Xiongcheng Li, Beijing, CN;

Xinlei Xu, Beijing, CN;

Lifeng Yang, Beijing, CN;

Changyu Feng, Beijing, CN;

Ruiyong Jia, Beijing, CN;

Assignee:

EMC IP Holding Company LLC, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/0802 (2016.01); G06F 12/0871 (2016.01); G06F 12/0855 (2016.01); G06F 12/0806 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G06F 12/0806 (2013.01); G06F 12/0857 (2013.01); G06F 12/0871 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/262 (2013.01); G06F 2212/284 (2013.01); G06F 2212/312 (2013.01); G06F 2212/461 (2013.01); G06F 2212/466 (2013.01); G06F 2212/608 (2013.01);
Abstract

Embodiments of the present disclosure relate to a method and device for cache management. The method includes: receiving an I/O request associated with a processor kernel; in response to first data that the I/O request is targeted for being missed in a cache, determining whether a first target address of the first data is recorded in one of a plurality of cache history lists; in response to the first target address not being recorded in the plurality of cache history lists, storing, in a first node of a first free cache history list, the first target address and an initial access count of the first target address, the first free cache history list being determined in association with the processor kernel in advance; and adding the first node to a first cache history list associated with the I/O request of the plurality of cache history lists.


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