The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2020
Filed:
Mar. 29, 2017
Veritas Technologies Llc, Mountain View, CA (US);
Rajesh Ghanekar, Pune, IN;
Tushar Shinde, Pune, IN;
Mukund Agrawal, Pune, IN;
Sreeharsha Sarabu, Pune, IN;
Vaibhav Gupta, Cupertino, CA (US);
Sandeep Jakka, Pune, IN;
Veritas Technologies LLC, Santa Clara, CA (US);
Abstract
The disclosed computer-implemented method for performing node failovers may include: (1) initiating, during a failover of a first node to a second node, a grace period for the first node and the second node; (2) writing a new lock, indicating an internet protocol (IP) address, to a memory device of the second node, while maintaining: (A) an old lock of the IP address in a memory device of the first node, and (B) locks of nodes other than the first and second nodes; (3) transferring the old lock from the first node to the new lock of the second node, where requests to change the locks of nodes other than the first and second nodes are denied during transferring; and (4) stopping the grace period. Various other methods, systems, and computer-readable media are also disclosed.