The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Feb. 17, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Harold W. Cain, III, Raleigh, NC (US);

Hubertus Franke, Cortlandt Manor, NY (US);

Charles R. Johns, Austin, TX (US);

Hung Q. Le, Austin, TX (US);

Ravi Nair, Briarcliff Manor, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 9/50 (2013.01); G06F 9/3012 (2013.01); G06F 9/30098 (2013.01); G06F 9/30123 (2013.01); G06F 9/384 (2013.01); G06F 9/3851 (2013.01); G06F 9/45516 (2013.01);
Abstract

A computer system includes a processor, main memory, and controller. The processor includes a plurality of hardware threads configured to execute a plurality of software threads. The main memory includes a first register table configured to contain a current set of architected registers for the currently running software threads. The controller is configured to change a first number of the architected registers assigned to a given one of the software threads to a second number of architected registers when a result of monitoring current usage of the registers by the software threads indicates that the change will improve performance of the computer system. The processor includes a second register table configured to contain a subset of the architected registers and a mapping table for each software thread indicating whether the architected registers referenced by the corresponding software thread are located in the first register table or the second register table.


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