The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2020
Filed:
Mar. 28, 2018
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventor:
Gordon I. Old, Edinburgh, GB;
Assignee:
XILINX, INC., San Jose, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 1/03 (2006.01); G06F 17/16 (2006.01); G06F 7/50 (2006.01); G06F 7/52 (2006.01); G06F 7/544 (2006.01); H03M 13/37 (2006.01);
U.S. Cl.
CPC ...
G06F 1/0307 (2013.01); G06F 7/50 (2013.01); G06F 7/52 (2013.01); G06F 7/544 (2013.01); G06F 17/16 (2013.01); H03M 13/3746 (2013.01);
Abstract
A circuit for implementing a polar decoder is described. The circuit includes a log-likelihood ratio processing circuit. A path metric update circuit is coupled to receive log-likelihood values for decoded bits from the log-likelihood ratio processing circuit, wherein the path metric circuit generates path metric values for the decoded bits. A partial sum calculation circuit is coupled to receive the path metrics; and a sort and cull circuit is coupled to receive a list of child path, wherein the sort and cull circuit eliminates invalid paths from the list of child paths. A method of implementing a polar decoder is also described.