The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Jun. 17, 2016
Applicant:

Signify Holding B.v., Eindhoven, NL;

Inventors:

Hongxin Chen, Shanghai, CN;

Hong Chen, Shanghai, CN;

Assignee:

SIGNIFY HOLDING B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/44 (2020.01); G01R 31/50 (2020.01); H05B 45/40 (2020.01); H05B 45/50 (2020.01);
U.S. Cl.
CPC ...
G01R 31/44 (2013.01); G01R 31/50 (2020.01); H05B 45/40 (2020.01); H05B 45/50 (2020.01);
Abstract

Apparatuses () for determining statuses of load circuits () comprise terminals () for exchanging current signals with current sources (). The load circuits () comprise D loads (L-L) in series combinations coupled to the terminals (). The apparatuses () further comprise capacitance circuits () comprising E monitor capacitances (C-C) with first contacts coupled to each other and to one of the terminals () and second contacts coupled to interconnections between the loads (L-L). The apparatuses () further comprise detection circuits () for detecting voltage signals present between the first and second terminals (), and derivation circuits () for deriving the statuses of the load circuits () from the detected voltage signals. Thereto, the derivation circuits () may calculate instantaneous capacities comprising steps indicative for said statuses of the load circuits (). The capacitance circuits () do advantageously not interfere with the load circuits () in steady-states, and may further comprise F parallel capacitances (C-C) in parallel to the loads (L-L).


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