The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2020

Filed:

Mar. 30, 2018
Applicant:

Kionix, Inc., Ithaca, NY (US);

Inventors:

Scott G. Adams, Ithaca, NY (US);

Charles W. Blackmer, Ithaca, NY (US);

Assignee:

Kionix, Inc., Ithaca, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); H01L 21/306 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
B81B 7/007 (2013.01); B81C 1/00301 (2013.01); H01L 21/30604 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5329 (2013.01); B81B 2207/096 (2013.01); B81C 2201/013 (2013.01);
Abstract

Disclosed is a method of forming an interconnect in a substrate having a first surface and a second surface. The method includes forming an insulating structure abutting the first surface and defining a closed loop around a via in the substrate and forming an insulating region abutting the second surface such that the insulating region contacts the insulating structure and separates the via from a bulk region of the substrate. Forming the insulating structure includes etching the substrate beginning from the first surface to form a trench, filling the trench to form a seam portion, and converting a first portion of the substrate to a first solid portion to form the closed loop.


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