The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Jul. 02, 2019
Applicant:

Nippon Pillar Packing Co., Ltd., Osaka, JP;

Inventors:

Takeshi Okunaga, Osaka, JP;

Akira Nakatsu, Osaka, JP;

Kojiro Iwasa, Osaka, JP;

Yusuke Natsuhara, Osaka, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 1/02 (2006.01); H01Q 1/32 (2006.01); H05K 3/46 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0243 (2013.01); H01Q 1/3233 (2013.01); H05K 1/024 (2013.01); H05K 1/0242 (2013.01); H05K 1/111 (2013.01); H05K 3/4652 (2013.01); H05K 3/4697 (2013.01); H05K 2201/10098 (2013.01); H05K 2203/1105 (2013.01);
Abstract

A method for producing a high frequency circuit board includes forming an antenna pattern on an upper surface of the provisional substrate. The method includes performing hot-press in a state where a thermoplastic resin and a provisional conductor are stacked on the upper surface of the provisional substrate, to form a first dielectric layer portion covering the antenna pattern. The method includes removing the provisional conductor and shaving the first dielectric layer portion to form a cavity to house an electronic component. The method includes mounting the electronic component on the antenna pattern in the cavity. The method includes performing hot-press in a state where a thermosetting resin and a ground conductor are stacked at an opening side of the cavity in the first dielectric layer portion, to form a second dielectric layer portion to embed the electronic component in the cavity. The method includes removing the provisional substrate.


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