The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Dec. 08, 2016
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, JP;

Inventors:

Norihiko Akashi, Chiyoda-ku, JP;

Hiroyuki Ono, Chiyoda-ku, JP;

Hiroshi Mihara, Chiyoda-ku, JP;

Yoshiaki Irifune, Chiyoda-ku, JP;

Daisuke Koyama, Chiyoda-ku, JP;

Yudai Yoneoka, Chiyoda-ku, JP;

Takashi Miyasaka, Chiyoda-ku, JP;

Shimpei Kasahara, Chiyoda-ku, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0224 (2013.01); H05K 2201/0979 (2013.01); H05K 2201/09263 (2013.01); H05K 2201/09609 (2013.01); H05K 2201/09672 (2013.01); H05K 2201/10053 (2013.01); H05K 2201/10189 (2013.01);
Abstract

A printed circuit substrate includes a circuit unit, a first main frame ground interconnection, a first sub frame ground interconnection spaced away from the first main frame ground interconnection in a first direction, and a first conductive via connecting the first main frame ground interconnection and the first sub frame ground interconnection to each other. In plan view from the first direction, a second outer periphery of the first sub frame ground interconnection is surrounded by a first outer periphery of the first main frame ground interconnection. Thus, a printed circuit substrate that can prevent the circuit unit from malfunctioning can be provided.


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