The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Nov. 11, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Bruno Miguel Vaz, Sao Domingos de Rana, PT;

John E. McGrath, Cahir, IE;

Conrado K. Mesadri, San Jose, CA (US);

Woon C. Wong, Dublin, CA (US);

Ali Boumaalif, City Cork Centre, IE;

Christopher Erdman, Dublin, IE;

Brendan Farley, Donobate, IE;

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/10 (2006.01); G01R 31/3185 (2006.01); H04L 12/43 (2006.01); H04L 12/433 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1215 (2013.01); G01R 31/318519 (2013.01); H03M 1/1071 (2013.01); H04L 12/43 (2013.01); H04L 12/433 (2013.01);
Abstract

An integrated circuit is described. The integrated circuit comprises an analog-to-digital converter circuit configured to receive an input signal at an input and generate an output signal at an output; and a monitor circuit coupled to the output of the analog-to-digital converter circuit, the monitor circuit configured to receive the output signal and to generate integration coefficients for the analog-to-digital converter circuit; wherein the integration coefficients are dynamically generated based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.


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