The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Feb. 20, 2020
Applicant:

Realtek Semiconductor Corp., Hsinchu, TW;

Inventor:

Chien-Wen Chen, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/087 (2006.01); H03L 7/18 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
H03L 7/087 (2013.01); H03L 7/0812 (2013.01); H03L 7/18 (2013.01);
Abstract

A phase-locked loop circuit includes a delay phase-locked loop and a sub-sampling phase-locked loop. The delay phase-locked loop phase locks a first reference clock and a second reference clock to an input clock, and includes a phase correction circuit, an integrator, a first sub-sampling phase detector, and a first charge pump. The sub-sampling phase-locked loop is configured to generate an output clock with a predetermined phase-locked loop frequency, and the output clock is phase-locked to the first reference clock, the sub-sampling phase-locked loop includes a second sub-sampling phase detector, a second charge pump, a phase frequency detecting circuit, a voltage controlled oscillator and a first frequency divider. The first sub-sampling phase detector and the second sub-sampling phase detector have a symmetric circuit structure, and a first charge pump circuit and a second charge pump circuit have a symmetric circuit structure.


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