The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Nov. 19, 2019
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Bert Sullam, Bellevue, WA (US);

Warren Snyder, Lake Stevens, WA (US);

Haneef Mohammed, Beaverton, OR (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/17 (2006.01); H01L 25/00 (2006.01); H03K 19/17736 (2020.01); H03K 19/177 (2020.01); H03K 19/17704 (2020.01); H03K 19/173 (2006.01); H03K 19/1776 (2020.01);
U.S. Cl.
CPC ...
H03K 19/17744 (2013.01); H03K 19/173 (2013.01); H03K 19/177 (2013.01); H03K 19/1776 (2013.01); H03K 19/17704 (2013.01);
Abstract

A method for operating a system level interconnect in an integrated circuit (IC) is provided in an example embodiment. The method comprises: writing, by a microcontroller in the IC, a first configuration value into a configuration register, where the first configuration value programs the system level interconnect to couple a first peripheral to a second peripheral; monitoring the IC to determine an operational state of the IC; and in response to determining a change in the operational state of the IC, writing by the microcontroller a second configuration value into the configuration register to dynamically change interconnections in the system level interconnect between the first peripheral and the second peripheral.


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