The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2020
Filed:
Sep. 12, 2018
Coolstar Technology, Inc., Santa Clara, CA (US);
Jessel T. Xavier, Sunnyvale, CA (US);
COOLSTAR TECHNOLOGY, INC., Santa Clara, CA (US);
Abstract
An ESD power clamp circuit includes first, second and third timing networks, first and second NMOS transistors and an enable circuit. The first timing network has a first time constant and detects a voltage transient between first and second voltage supply nodes having a rise time less than the first time constant. The first NMOS transistor has a gate connected with an output of the first timing network and a source connected with a gate of the second NMOS transistor. The second NMOS transistor has a drain connected with the first voltage supply node and a source connected with the second voltage supply node. The second timing network is coupled with the gate of the second NMOS transistor and has a second time constant that is greater than a duration of an ESD event. The third timing network is coupled with the enable circuit and has a third time constant, the third timing network generating a first control signal based on the third time constant. The enable circuit inhibits clamping action of the clamp circuit based on the first control signal.