The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Jun. 07, 2018
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Mahmoud Shehab Mohammad Al-Sa'di, Kranenburg, DE;

Petrus Hubertus Cornelis Magnee, Malden, NL;

Ihor Brunets, Kleve, DE;

Jan Willem Slotboom, Eersel, NL;

Tony Vanhoucke, Bierbeek, BE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1087 (2013.01); H01L 21/76227 (2013.01); H01L 21/823437 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/0692 (2013.01); H01L 29/0847 (2013.01); H01L 29/41758 (2013.01); H01L 29/7801 (2013.01); H01L 29/7833 (2013.01); H01L 29/7835 (2013.01);
Abstract

A semiconductor switch device and a method of making the same. The device includes a semiconductor substrate having a major surface. The device also includes a first semiconductor region located in the substrate beneath the major surface. The device includes an elongate gate located on the major surface. The device also includes a source region and a drain region located in the first semiconductor region adjacent respective first and second elongate edges of the gate. The device also includes electrical contacts for the source and drain regions. The contacts include at least two contacts located on either the source region or the drain region, which are spaced apart along a direction substantially parallel the elongate edges of the gate. The device further includes an isolation region located between the at least two contacts. The isolation region extends through the source/drain region from the major surface to the first semiconductor region.


Find Patent Forward Citations

Loading…