The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2020
Filed:
Sep. 17, 2019
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Tae-sung Kim, Cheonan-si, KR;
Cheol-woo Lee, Gwangmyeong-si, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 21/56 (2006.01); H01L 23/367 (2006.01); H01L 23/552 (2006.01); H01L 23/29 (2006.01); H01L 25/00 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/56 (2013.01); H01L 23/295 (2013.01); H01L 23/3675 (2013.01); H01L 23/3677 (2013.01); H01L 23/552 (2013.01); H01L 25/50 (2013.01); H01L 21/4882 (2013.01); H01L 23/3128 (2013.01); H01L 23/367 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/15311 (2013.01);
Abstract
A semiconductor package including a package base substrate; at least one semiconductor chip on the package base substrate; a heat sink attached on the at least one semiconductor chip, the heat sink including a base and a plurality of protrusion patterns on a top of the base; and a molding covering a top of the package base substrate, a side surface of the at least one semiconductor chip, and a side surface of the heat sink without covering a top of the heat sink.