The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2020

Filed:

Oct. 19, 2018
Applicant:

Socionext Inc., Kanagawa, JP;

Inventors:

Toshihiro Nakamura, Yokohama, JP;

Isao Motegi, Yokohama, JP;

Noriyuki Shimazu, Yokohama, JP;

Masanobu Hirose, Yokohama, JP;

Taro Fukunaga, Yokohama, JP;

Assignee:

SOCIONEXT INC., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49811 (2013.01); H01L 24/06 (2013.01); H01L 24/49 (2013.01); H01L 24/48 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/06 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06132 (2013.01); H01L 2224/06133 (2013.01); H01L 2224/06135 (2013.01); H01L 2224/06177 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48108 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/4917 (2013.01); H01L 2224/49113 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/49177 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.


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