The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2020
Filed:
May. 17, 2019
3-5 Power Electronics Gmbh, Dresden, DE;
Volker Dudek, Ettlingen, DE;
3-5 Power Electronics GmbH, Dresden, DE;
Abstract
A method and stacked semiconductor device having a top surface, a bottom surface, and at least one side surface that connects the top surface with the bottom surface. The bottom surface is formed of a substrate layer or a rear side contact layer arranged below the substrate layer. On the substrate layer, a first semiconductor layer of a first conductivity type is arranged and on the first semiconductor layer at least one second semiconductor layer of a second conductivity type is arranged. The first and second semiconductor layers are formed of a III-V material or consist of a III-V material. The first and second conductivity types are different. The top surface is at least partially formed by a passivation layer. Along the side surface, an amorphized and/or insulating region extending to a depth is formed, and the depth is perpendicular or substantially perpendicular to the layer stack.